1. Field of the Invention
The present invention relates to a DLL (Delay Locked Loop) circuit and a semiconductor device including the same, and, more particularly relates to a DLL circuit capable of locking a high frequency clock signal and a semiconductor device including the same. The present invention also relates to a data processing system including such a semiconductor device.
2. Description of Related Art
In recent years, as a main memory for a personal computer or the like, a synchronous memory device that performs an operation synchronous with a clock signal is widely used. Particularly, in a DDR (Double Data Rate) synchronous memory device, there is a need of precisely synchronizing input/output data with an external clock signal, and thus a DLL circuit that generates an internal clock signal synchronous with the external clock signal is required. Japanese Patent Application Laid-open No. 2007-243735 discloses an example of such a DLL circuit.
The DLL circuit has a function of adjusting a position of a rising edge of the internal clock signal and a function of adjusting a position of a falling edge of the internal clock signal. With these functions, a phase of the external clock signal and that of the internal clock signal are matched. The rising edge of the internal clock signal is regulated by a Rise clock signal generated within the DLL circuit, and the falling edge of the internal clock signal is regulated by a Fall clock signal generated within the DLL circuit.
FIG. 5A is a timing chart for explaining an operation of the DLL circuit.
In an example in FIG. 5A, an active edge (in this example, a rising edge) of the Rise clock signal is advanced relative to the rising edge of an external clock signal CK. An active edge (in this example, a rising edge) of the Fall clock signal is delayed relative to the falling edge of the external clock signal CK. In this case, the phase of the Rise clock signal is adjusted in a delaying direction, and the phase of the Fall clock signal is adjusted to an advancing direction. The Rise clock signal and the Fall clock signal thus adjusted are combined within the DLL circuit, and thereby the internal clock signal is reproduced.
However, as in the example, when the phase of the Rise clock signal is adjusted in a delaying direction and the phase of the Fall clock signal is adjusted in an advancing direction, a clock width of the generated internal clock signal becomes small. That is, as compared to the clock width before the adjustment, the clock width of the internal clock signal is smaller by two pitches. Such a phenomenon does not cause a serious problem as far as a clock cycle for one adjustment pitch is sufficiently long. However, when a frequency of the external clock signal is high, and if the clock width of the internal clock signal becomes narrower by two pitches all at once, the clock width becomes too small, and thus it results in a short pulse, which can sometimes cause disappearance of the pulse.
Such a problem also occurs in a case contrary to the above example. That is, as shown in FIG. 5B, when the active edge of the Rise clock signal is delayed relative to the rising edge of the external clock signal CK and the active edge of the Fall clock signal is advanced relative to the falling edge of the external clock signal CK, the phase of the Rise clock signal is adjusted in an advancing direction and the phase of the Fall clock signal is adjusted in a delaying direction. In this case, the clock width of the generated internal clock signal is increased by two pitches all at once, as compared to the clock width before the adjustment. Accordingly, when the frequency of the external clock signal is high, the clock width of the internal clock signal becomes too large. As a result, a pulse on a low side is sometimes short-pulse, which can cause disappearance of the pulse.
Thus, in the conventional DLL circuit, when the adjusting direction of the Rise clock signal and the adjusting direction of the Fall clock signal are opposite to each other, there is a probability of disappearance of the pulse of the internal clock signal. When such a pulse disappearance occurs, the DLL circuit is not able to operate any longer, and thus the system requires resetting.